The present invention relates to a method of manufacturing a semiconductor device, particularly, an insulated gate (MOS) field effect semiconductor device having a lightly doped drain (referred to as LDD hereinafter) structure.
FIGS. 1A to 1C are cross sections showing main steps of a conventional manufacturing method of a semiconductor device of this type.
In FIGS. 1A to 1C, a gate insulating film 2 and a gate electrode 3 are formed on a p-type silicon substrate 1, and a low density n-type region 4 used to form a source and a drain is formed by the ion-injection of a low density n-type impurity (1) under a low acceleration voltage while using the gate electrode as a mask (FIG. 1A). The ion-injection may be performed after the insulating film 2, except a portion thereof beneath the gate electrode 3, is removed as shown in FIG. 1A. Then, as shown in FIG. lB, an oxide film 9 is deposited using low pressure chemical vapor deposition (LPCVD). Thereafter, as shown in FIG. 1C, the oxide film 9, except a portion 10 thereof on a gate sidewall is removed by anisotropic reactive ion etching (RIE). Next a high density n-type region 5 is formed by ion injection of a high density n-type impurity (I) while using the gate electrode and the oxide portion as a mask. Thus, the LDD structure is formed.
In the conventional LDD structure, it is difficult to determine the time at which the anisotropic RIE should be terminated. That is, since the oxide portion 10 on the sidewall is used as a mask in subsequent steps, the width L of the oxide portion is very important. If its etching is not terminated properly, the width L of the oxide portion becomes variable, and sometimes even the source/drain region is etched away.
Further, if the low concentration n-type region 4 is formed by injecting, for example, phosphorous at 1.times.10.sup.14 ions/cm.sup.2 under 30 KeV, that region cannot be made amorphous. Therefore; a crystalline structure must be recovered by high temperature annealing; otherwise leakage currents may occur. Such annealing prevents the formation of shallow junctions, making minimization of the size of the device impossible.
Another problem encountered in the conventional LDD structure prepared using an oxide film portion on the gate sidewall is that hot carriers may be injected into the oxide film portion 10 during a MOSFET operation, whereupon the low concentration n-type region 4 is depleted, causing the resistance thereof to be increased, and resulting in degradation of the transconductance of the device. Further, if it is attempted to minimize the size of the device by making the junctions shallower, resistances of the drain/source region, gate electrode and contacts are increased.